IEEE Std 1581 - IEEE Standard for Static Component Interconnection Test Protocol and Architecture

IEEE 1581 simplifies the testing of devices that do not contain IEEE Std 1149.1 compliant technology in the devices. Primarily, this standard addresses the testing of memory device connections to ensure the memory modules are installed properly on the circuit board. JEDEC has chosen the test method defined by this standard for testing of DDR4 memory devices as a required test feature of all DDR4 memory modules.

The following is an excerpt from the IEEE Std 1581-2011 publication.

Scope

This standard defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1TM) 1 is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.

Purpose

There is currently no defined, independent standard for test technology in memory devices. Each vendor is free in the way of implementing test hardware functionality in their ICs to support connectivity tests. Without an independent standard, testability is reduced, and test coverage may not be complete — making the test technology less useful for others.

This standard will improve interconnect testing for discrete memory devices by specifying implementation rules for test logic and test mode entry/exit methods included in memory ICs as guidance both to IC vendors implementing the standard and to test equipment manufacturers supporting this standard. The standard is aimed at ICs that are otherwise not provisioned with design for testability (DFT) for any reason, targeting primarily memory devices but also allowing for implementation in other devices, while supporting the highest fault coverage and pin-level diagnostics of board-level connectivity faults on such devices.

This is gallery of key concepts being investigated by the working group.

https://standards.ieee.org/standard/1581-2011.html http://grouper.ieee.org/groups/1581/